TMS320DM647 datasheet(127/182 Pages) TI

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6.14 Serial Peripheral Interface Port (SPI)

6.14.1 SPI Device-Specific Information

Peripheral

ConfigurationBus

Interruptand

DMA Requests

16-BitShiftRegister

16-BitBuffer

16-BitEmulationBuffer

GPIO

Control

(allpins)

State

Machine

Clock

Control

SPIDO

SPIDI

SPICSx

SPICLK

SLAVESPI

MASTERSPI

SPIDO

SPIDI

SPICLK

Optional − SlaveChipSelect

SPICSx

SPICLK

SPIDI

SPIDO

TMS320DM647/TMS320DM648

Digital Media Processor

www.ti.com

SPRS372B – MAY 2007 – REVISED APRIL 2008

Figure 6-35 is a block diagram of the SPI module, which is a simple shift register and buffer plus control

logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end

of transmission. The SPI can operate only as a master, in which case, it initiates a transfer and drives the

SPICLK pin. Four clock phase and polarity options are supported as well as many data formatting options.

Figure 6-35. Block Diagram of SPI Module

The SPI supports 3- and 4-pin operation with three basic pins (SPICLK, SPIDO, and SPIDI) and two

optional pins (SPICSx).

The optional SPICSx (Slave Chip Select) pin is most useful to enable in master mode when there are

more than one slave devices on the same SPI port. The device only shifts data and drives the SPIDI pin

when SPICSx is held low.

Figure 6-36. Illustration of SPI Master-to-SPI Slave Connection

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Peripheral Information and Electrical Specifications

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