TMS320DM647 datasheet(120/182 Pages) TI

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6.11.3.3 VCLKIN Timing (Video Display Mode)

VPxCLKINx

6.11.3.4 Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372B – MAY 2007 – REVISED APRIL 2008

www.ti.com

Table 6-50. Timing Requirements for Video Display Mode for VPxCLKINx(1) (see Figure 6-30)

-720

-900

NO.

UNIT

MIN

MAX

tc(VKI)

Cycle time, VPxCLKINx

tw(VKIH)

Pulse duration, VPxCLKINx high

4.1

tw(VKIL)

Pulse duration, VPxCLKINx low

4.1

tt(VKI)

Transition time, VPxCLKINx

(1)

The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

Figure 6-30. Video Port Display VPxCLKINx Timing

and VPxCLKOUTx (Video Display Mode)

Table 6-51. Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to

VPxCLKINx and VPxCLKOUTx (see Figure 6-31)

-720

-900

NO.

UNIT

MIN

MAX

tsu(VCTLV-VKIH)

Setup time, VPxCTLx valid before VPxCLKINx high

2.4

th(VCTLV-VKIH)

Hold time, VPxCTLx valid after VPxCLKINx high

0.5

tsu(VCTLV-VKOH)

Setup time, VPxCTLx valid before VPxCLKOUTx high(1)

7.4

th(VCTLV-VKOH)

Hold time, VPxCTLx valid after VPxCLKOUTx high(1)

–0.9

(1)

Assuming non-inverted VPxCLKOUTx signal.

Peripheral Information and Electrical Specifications

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