M54/74HC563

M54/74HC573

October 1993

HC563 INVERTING - HC573 NON INVERTING

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT

B1R

(Plastic Package)

ORDER CODES :

M54HCXXXF1R

M74HCXXXM1R

M74HCXXXB1R

M74HCXXXC1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTION (top view)

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

15 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS563/573

DESCRIPTION

The M54/74HC563 and M54HC573 are high speed

CMOS OCTAL LATCH WITH 3-STATE OUTPUTS

fabricated with in silicon gate C

These ICs archive the high speed operation similar

to equivalent LSTTL while maintaning the CMOS

low power dissipation.

These 8 bit D-Type latches are controlled by a latch

enable input (LE) and a output enable input (OE).

While the LE input is held at a high level, the Q

outputs will follow the data input precisely or

inversely. When the LE is taken low, the Q outputs

will be latched precisely or inversely at the logic level

of D input data. While the OE input is at low level,

the eight outputs will be in a normal logic state (high

or low logic level) and while high level the outpts will

be in a high impedance state.

The

application

designer

has

a

choise

of

combination of inverting and non inverting outputs.

The three state output configuration and the wide

choise of outline make bus organized system

simple.

All inputs are equipped with protection circuits

against discharge and transient excess voltage.

HC563

HC573

HC563

HC573

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