HT9B95B datasheet(16/32 Pages) HOLTEK

16 / 32 page

Rev. 1.10

November 25, 2015

HT9B95A/B/G

• Display RAM Page Write Operation

After a START condition the slave address with

a R/W bit is placed on the bus followed with

the specified display RAM Register Address of

which the contents are written into the internal

address pointer. The data to be written into the

memory will be transmitted next. The internal

address pointer will be incremented by 1 after

a 8-bit data is shifted in. Then the acknowledge

clock pulse will be received after an 8-bit data is

shifted. After the internal address point reaches the

maximum available address, 22H, 15H or 26H, the

address pointer will be reset to 00H. It is strongly

recommended to write the display RAM data from

address 00H to maximum available address using

the Display RAM Page Write Operation.

Part No. Duty Maximum Available Address

HT9B95A

1/8

22H

HT9B95B

HT9B95G

1/4

15H

1/8

26H

Display RAM Maximum Available Address

Read Operation

• Display RAM Read Operation

The master reads the display RAM data after

setting the slave address. Following the R/W

bit (=”0”) is an acknowledge bit and the register

address byte which is written to the internal address

pointer. After the start address of the read operation

has been configured, another START condition and

the slave address transferred on the bus followed

by the R/W bit (=”1”). Then the MSB of the data

which was addressed is transmitted first on the

I2C bus. The address pointer is only incremented

by 1 after the reception of an acknowledge clock.

After reaching the maximum available address, the

address pointer will be reset to 00H. The C bit in

the register address byte can be set to “1” or “0”.

This read operation will continue until the master

sends a STOP condition. The maximum available

address is summarized in the above section.

Slave Address

ACK

Address n

ACK

Data byte

ACK

Data byte

nth data

ACK

RAM Address byte

( n+1)th data

Nth data

C bit

I2C Interface N Bytes Display RAM Data Write Operation

ACK

Write

Slave Address

Data byte

NACK

1st data

Data byte

ACK

Nth data

Data byte

2nd data

ACK

Device Address

Read

ACK

RAM Address byte

C bit

Display RAM Read Operation

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