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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7LITE1XB датащи(PDF) 87 Page - STMicroelectronics |
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ST7LITE1XB датащи(HTML) 87 Page - STMicroelectronics |
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87 / 157 page  ST7LITE1xB 87/157 SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR regis- ter (see Figure 56). In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register. In Master mode: –SS internal must be held high continuously In Slave Mode: There are two cases depending on the data/clock timing relationship (see Figure 55): If CPHA = 1 (data latched on second clock edge): –SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to VSS, or made free for standard I/O by manag- ing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR register) If CPHA = 0 (data latched on first clock edge): –SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 11.4.5.3). Figure 55. Generic SS Timing Diagram Figure 56. Hardware/Software Slave Select Management MOSI/MISO Master SS Slave SS (if CPHA = 0) Slave SS (if CPHA = 1) Byte 1 Byte 2 Byte 3 1 0 SS internal SSM bit SSI bit SS external pin 1 |
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