C8051F310 datasheet(8/228 Pages) SILABS

8 / 228 page

C8051F310/1/2/3/4/5/6/7

Rev. 1.7

7. Comparators

Figure 7.1. Comparator0 Functional Block Diagram ................................................ 69

Figure 7.2. Comparator1 Functional Block Diagram ................................................ 70

Figure 7.3. Comparator Hysteresis Plot ................................................................... 71

8. CIP-51 Microcontroller

Figure 8.1. CIP-51 Block Diagram............................................................................ 79

Figure 8.2. Memory Map .......................................................................................... 85

9. Reset Sources

Figure 9.1. Reset Sources...................................................................................... 105

Figure 9.2. Power-On and VDD Monitor Reset Timing ........................................... 106

10. Flash Memory

Figure 10.1. Flash Program Memory Map.............................................................. 113

11. External RAM

12. Oscillators

Figure 12.1. Oscillator Diagram.............................................................................. 121

Figure 12.2. 32.768 kHz External Crystal Example................................................ 126

13. Port Input/Output

Figure 13.1. Port I/O Functional Block Diagram ..................................................... 129

Figure 13.2. Port I/O Cell Block Diagram ............................................................... 130

Figure 13.3. Crossbar Priority Decoder with No Pins Skipped ............................... 131

Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 132

14. SMBus

Figure 14.1. SMBus Block Diagram ....................................................................... 145

Figure 14.2. Typical SMBus Configuration ............................................................. 146

Figure 14.3. SMBus Transaction ............................................................................ 147

Figure 14.4. Typical SMBus SCL Generation......................................................... 151

Figure 14.5. Typical Master Transmitter Sequence................................................ 157

Figure 14.6. Typical Master Receiver Sequence.................................................... 158

Figure 14.7. Typical Slave Receiver Sequence...................................................... 159

Figure 14.8. Typical Slave Transmitter Sequence.................................................. 160

15. UART0

Figure 15.1. UART0 Block Diagram ....................................................................... 163

Figure 15.2. UART0 Baud Rate Logic .................................................................... 164

Figure 15.3. UART Interconnect Diagram .............................................................. 165

Figure 15.4. 8-Bit UART Timing Diagram............................................................... 165

Figure 15.5. 9-Bit UART Timing Diagram............................................................... 166

Figure 15.6. UART Multi-Processor Mode Interconnect Diagram .......................... 167

16. Enhanced Serial Peripheral Interface (SPI0)

Figure 16.1. SPI Block Diagram ............................................................................. 173

Figure 16.2. Multiple-Master Mode Connection Diagram ....................................... 176

Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 176

Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 176

Figure 16.5. Master Mode Data/Clock Timing ........................................................ 178

Figure 16.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 179

Figure 16.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 179

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