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XISO6441DFPR датащи(PDF) 33 Page - Texas Instruments |
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XISO6441DFPR датащи(HTML) 33 Page - Texas Instruments |
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33 / 56 page ![]() 9.4.2 Layout Example I/O pins routed on top or on alternate layers (with vias) Solid ground planes reduce ground inductance and dissipate heat through PCB Solid supply islands reduce inductance because large peak currents flow into the VCC pin 1 2 3 4 5 7 8 16 9 6 15 14 13 12 10 11 GND2 GND1 Ground Plane (2 nd Layer) Ground Plane (2 nd Layer) GND1 GND2 EN1 EN2 0.1µF capacitance 0.5mm maximum from VCC1 to GND1, low inductance vias to ground plane 0.1µF capacitance 0.5mm maximum from VCC2 to GND2, low inductance vias to ground plane low inductance vias to ground plane at GND pins low inductance vias to ground plane at GND pins VCC1 VCC2 Figure 9-6. Layout Example 10 mils 10 mils 40 mils FR-4 0r ~ 4.5 Keep this space free from planes, traces, pads, and vias Ground plane Power plane Low-speed traces High-speed traces Figure 9-7. Layout Example PCB cross section www.ti.com ISO6440, ISO6441, ISO6442 SLLSG01B – SEPTEMBER 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: ISO6440 ISO6441 ISO6442 |
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