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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M25P05-AVMB6TP датащи(PDF) 13 Page - Numonyx B.V |
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M25P05-AVMB6TP датащи(HTML) 13 Page - Numonyx B.V |
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13 / 52 page  M25P05-A Operating features 13/52 4.5 Status register The status register contains a number of status and control bits, as shown in Table 6, that can be read or set (as appropriate) by specific instructions. 4.5.1 WIP bit The write in progress (WIP) bit indicates whether the memory is busy with a write status register, program or erase cycle. 4.5.2 WEL bit The write enable latch (WEL) bit indicates the status of the internal write enable latch. 4.5.3 BP1, BP0 bits The block protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against program and erase instructions. 4.5.4 SRWD bit The status register write disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The status register write disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the hardware protected mode. In this mode, the non-volatile bits of the status register (SRWD, BP1, BP0) become read-only bits. |
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