M50FW080 datasheet(15/56 Pages) STMICROELECTRONICS

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M50FW080

Signal descriptions

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2.2

Address/Address Multiplexed (A/A Mux) signal descriptions

For the Address/Address Multiplexed (A/A Mux) Interface see Figure 2 and Table 2.

2.2.1

Address inputs (A0-A10)

The Address Inputs are used to set the Row Address bits (A0-A10) and the Column

Address bits (A11-A19). They are latched during any bus operation by the Row/Column

Address Select input, RC.

2.2.2

Data inputs/outputs (DQ0-DQ7)

The Data Inputs/Outputs hold the data that is written to or read from the memory. They

output the data stored at the selected address during a Bus Read operation. During Bus

Write operations they represent the commands sent to the Command Interface of the

internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write

operation.

2.2.3

Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

2.2.4

Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

2.2.5

Row/Column Address Select (RC)

The Row/Column Address Select input selects whether the Address Inputs should be

latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A19). The

Row Address bits are latched on the falling edge of RC whereas the Column Address bits

are latched on the rising edge.

2.2.6

Ready/Busy Output (RB)

The Ready/Busy pin gives the status of the memory’s Program/Erase Controller. When

Ready/Busy is Low, VOL, the memory is busy with a Program or Erase operation and it will

not accept any additional Program or Erase command except the Program/Erase Suspend

command. When Ready/Busy is High, VOH, the memory is ready for any Read, Program or

Erase operation.

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