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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M491B датащи(PDF) 7 Page - STMicroelectronics |
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M491B датащи(HTML) 7 Page - STMicroelectronics |
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7 / 16 page  V A D/A Converter VC Varicap VB VB VA VC down-up Figure 6 PIN 6 : DIGITAL AFT STATUS OUTPUT (see Figure 7) This output shows the status of the digital AFT. It is low when the digital AFT is enabled and it can directly drive a LED. The output consists of an open drain transistor. PINS 7 & 8 : OSCILLATOR INPUT/OUTPUT (see Figure 8) The frequency of the clock oscillator should be between 445 and 510kHz using a low-cost ceramic resonator. In these conditions the value of the reference frequency of the transmitter can be in the same range. In other words the transmitter and the receiver can operate with different reference fre- quencies. 6 max. 13.2V Figure 7 7 8 455 to 510kHz 100pF 100pF Figure 8 PIN 9 : VDD The supply voltage has to be comprised in the range 4.75 to 5.25V. When it is applied an internal power on reset of 0.5s is generated. The memory position 1 is automatically read if the mains on option input (Pin 25) is grounded. PIN 10 : TEST This pin is used for testing and has to be connected to VSS. PIN 11 : I.R. SIGNAL INPUT (see Figure 9) The integrated receiver decodes signals transmit- ted by M708, address 9. The minimum signal to be applied is 0.5V peak-to- peak. (AC-coupled). The receiver input section performs the following tests on the incoming signal to achieve the neces- sary noise immunity : - measurement of the pulse distance (time base synchronization) M491B 7/16 |
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