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M48T59, M48T59Y, M48T59V

Table 10. Write Mode AC Characteristics

2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Symbol

Parameter

M48T59/M48T59Y/M48T59V

Unit

-70

Min

Max

Write Cycle Time

70

ns

Address Valid to Write Enable Low

0

ns

Address Valid to Chip Enable Low

0

ns

Write Enable Pulse Width

50

ns

Chip Enable Low to Chip Enable High

55

ns

Write Enable High to Address Transition

0

ns

Chip Enable High to Address Transition

0

ns

Input Valid to Write Enable High

30

ns

Input Valid to Chip Enable High

30

ns

Write Enable High to Input Transition

5

ns

Chip Enable High to Input Transition

5

ns

(1, 2)

Write Enable Low to Output Hi-Z

25

ns

Address Valid to Write Enable High

60

ns

Address Valid to Chip Enable High

60

ns

(1, 2)

Write Enable High to Output Transition

5

ns

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT™ read/write memory cells.

The M48T59/59Y/59V includes a clock control cir-

cuit which updates the clock bytes with current in-

formation once per second. The information can

be accessed by the user in the same manner as

any other location in the static memory array.

The M48T59/59Y/59V also has its own Power-fail

Detect circuit. The control circuitry constantly mon-

itors the single 5V supply for an out of tolerance

write protects the SRAM, providing a high degree

of data security in the midst of unpredictable sys-

below approximately 3V, the control circuitry con-

nects the battery which maintains data and clock

operation until valid power returns.

READ MODE

The M48T59/59Y/59V is in the Read Mode when-

ever W (Write Enable) is high and E (Chip Enable)

is low. The unique address specified by the 13 Ad-

dress Inputs defines which one of the 8,192 bytes

of data is to be accessed. Valid data will be avail-

able at the Data I/O pins within Address Access

stable, providing that the E and G access times

are also satisfied. If the E and G access times are

not met, valid data will be available after the latter

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

puts are changed while E and G remain active,

output data will remain valid for Output Data Hold

Address Access.