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November 20, 2023

8P34S2108 Datasheet

Wiring the Differential Input to Accept Single-ended Levels

Figure 3 shows an example of how a differential input can be wired to accept single-ended levels. To satisfy the VCMR requirement, the

reference voltage V1 is set to 1.2V which is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter

noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be

adjusted to position the V1 to meet the VCRM requirement. For example, if the input clock swing is 1.8V and VDD = 1.8V, R1 and R2

value should be adjusted to set V1 at 1.2V in this example. The values below are for when both the single-ended swing and VDD are at

the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs)

equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in

one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance and the signal DC offset after AC coupling

should be equal to V1, i.e. 1.2V in this example. For most Zo = 50Ω applications, R3 = 75Ω and R4 can be 130Ω. By keeping the same

R3/R4 ratio, the values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using

single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the input can handle larger

amplitude signaling, it is recommended that the amplitude be reduced. For single-ended applications, the swing can be larger. Make sure

the single-ended logic high and logic low signal operates within specification limit. Though some of the recommended components might

not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are

characterized and guaranteed by using a differential signal.

Figure 3. Example Schematic for Wiring a Differential Input to Accept Single-ended Levels

 

R4

150

VDD

V1

LVCMOS Driv er

R1

1.5k

C2

0.1uF

Ro

C1

0.1uF

R2

2.6k

Zo = 50

Receiv er

+

-

R5

Ro+Rs=Zo

VDD

R3

75