MSC8103RMSLASHD datasheet(13/104 Pages) FREESCALE

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System Bus, HDI16, and Interrupt Signals

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

1-9

D[32–47]

HD[0–15]

Input/Output

Data Bus Bits 32–47

In write transactions the bus master drives the valid data on this bus. In read transactions the slave

drives the valid data on this bus.

Host Data2

When the HDI16 interface is enabled, these signals are lines 0-15 of the bidirectional tri-state data

bus.

D[48–51]

HA[0–3]

Input/Output

Input

Data Bus Bits 48–51

In write transactions the bus master drives the valid data on these pins. In read transactions the

slave drives the valid data on these pins.

Host Address Line 0–33

When the HDI16 interface bus is enabled, these lines address internal host registers.

D52

HCS1

Input/Output

Input

Data Bus Bit 52

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Chip Select3

When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select

is a logical OR of HCS1 and HCS2.

D53

HRW

HRD/HRD

Input/Output

Input

Data Bus Bit 53

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Read Write Select3

When the HDI16 interface is enabled in Single Strobe mode, this is the read/write input (HRW).

Host Read Strobe3

When the HDI16 is programmed to interface with a double data strobe host bus, this pin is the read

data strobe Schmitt trigger input (HRD/HRD). The polarity of the data strobe is programmable.

D54

HDS/HDS

HWR/HWR

Input/Output

Input

Data Bus Bit 54

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Data Strobe3

When the HDI16 is programmed to interface with a single data strobe host bus, this pin is the data

strobe Schmitt trigger input (HDS/HDS). The polarity of the data strobe is programmable.

Host Write Data Strobe3

When the HDI16 is programmed to interface with a double data strobe host bus, this pin is the write

data strobe Schmitt trigger input (HWR/HWR). The polarity of the data strobe is programmable.

D55

HREQ/HREQ

HTRQ/HTRQ

Input/Output

Output

Data Bus Bit 55

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Request3

When the HDI16 is programmed to interface with a single host request host bus, this pin is the host

request output (HREQ/HREQ). The polarity of the host request is programmable. The host request

may be programmed as a driven or open-drain output.

Transmit Host Request3

When the HDI16 is programmed to interface with a double host request host bus, this pin is the

transmit host request output (HTRQ/HTRQ). The signal can be programmed as driven or open

drain. The polarity of the host request is programmable.

Table 1-5.

System Bus, HDI16, and Interrupt Signals (Continued)

Signal

Data Flow

Description

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