MSC8103SLASHD datasheet(53/104 Pages) FREESCALE

53 / 104 page

AC Timings

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

2-13

2.6.4.4 Hardware Reset Configuration

Hardware reset configuration is enabled if HPE is sampled low at the rising edge of PORESET. The value driven on

RSTCONF

while PORESET changes from assertion to deassertion determines the MSC8103 configuration. If

RSTCONF

is deasserted (driven high) while PORESET changes, the MSC8103 acts as a configuration slave. If

RSTCONF

is asserted (driven low) while PORESET changes, the MSC8103 acts as a configuration master. Section

2.6.4.4, Hardware Reset Configuration, explains the configuration sequence and the terms “configuration master”

and “configuration slave.”

Directly after the deassertion of PORESET and choice of the reset operation mode as configuration master or

configuration slave, the MSC8103 starts the configuration process. The MSC8103 asserts HRESET and SRESET

throughout the power-on reset process, including configuration. Configuration takes 1024 CLOCKIN cycles, after

which MODCK[1–3] are sampled to determine the MSC8103’s working mode.

Next, the MSC8103 halts until the SPLL locks. The SPLL locks according to MODCK[1–3], which are sampled, and

to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800 reference clocks, which is the

clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8103 are enabled.

If the DLLDIS bit in the reset configuration word is reset, the DLL starts the locking process after the SPLL is

locked. During PLL and DLL locking, HRESET and SRESET are asserted. HRESET remains asserted for another 512

BUS clocks and is then released. The SRESET is released three bus clocks later. If the DLLDIS bit in the reset

configuration word is set, the DLL is bypassed and there is no locking process, thus saving the DLL locking time.

Figure 2-8 shows the power-on reset flow.

Figure 2-8.

Hardware Reset Configuration Timing

PORESET

Internal

HRESET

Input

SRESET

RSTCONF is sampled for

master/slave determination

MODCK[1–3] are sampled.

MODCK_H bits are ready

for PLL.

HRESET/SRESET are

extended for 512/515 bus

clocks, respectively, from PLL

and DLL Lock time.

In reset configuration mode:

reset configuration sequence

occurs in this period.

PLL locks after

800 SPLLMFCLKs. DLL

locks 3073 bus clocks after

PLL is locked.

When DLL is disabled, reset

period is shortened by 3073

bus clocks.

Output (I/O)

asserted for

min 16

CLKIN.

PLL locked

DLL locked

MSC8103/D датащи(PDF) 53 Page - Freescale Semiconductor, Inc

MSC8103/D датащи(HTML) 53 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL