M3488 datasheet(12/18 Pages) STMICROELECTRONICS

12 / 18 page

Internal time bases are forced by synchronism to an

assigned count number in order to restore channels

and bit sequential addressing to a known state.

Count difference between the bases is 32, corre-

spondingto two time slots, that is the minimum PCM

propagation time, or latency time.

INP PCM 7 to INP PCM 0

PCM input busses or pins ; they accept a standard

2Mbit/s rate. Bit 1 (sign bit) is the first of the serial

sequence ; in a parallel conversion it is left adjusted

as the most significant digit.

OUT PCM 7 to OUT PCM 0

PCM output busses or pins ; bit rate and organiza-

tion are the same as input pins.

Output buffers are open drain CMOS .

The device drives the output channels theoretically

one bit time before they can be exploited as logical

input channels (bit and slot compatibility is pre-

served): this feature allows inputs and outputs to be

tied together cancelling any analog delay of digital

outputs up to

tDEL max =tbit -tPD(PCM)max +tPD(PCM)min

MIXED RD and WR OPERATIONS

In principle RD and WR operations are allowed in

any order within specification constraints.

In practive, only one control pin is low at any given

time when CS1 and CS2 are enabled.

If by mistake or hardware failure both RD and WR

pins are low, the interface bus is internally pushed

to tristate condition as long as WR is held low and

input registers are protected.

Registers OR1 and OR2 can be read in any order

with a single RD strobe using C/D as multiplexing

control ; never the less this procedure is not recom-

mended because the device is directed for instruc-

tion flow only according to data latched by RD rising

edge.

Multiple RD operationsof the same kind are allowed

without affecting the instruction flow : only ”new”

OR1 or OR2 read operations step the flow.

Input and output registers are held for sure in the

previous state for the first 3 cycles following an op-

code or an OR2 read.

FUNCTIONAL DESCRIPTION OF SPECIFIC MICROPROCESSOR OPERATIONS

The device, under microprocessor control, performs

the following instructions :

1 CHANNEL CONNECTION

2 CHANNEL DISCONNECTION

3 LOADING OF A BYTE ON A PCM OUTPUT

CHANNEL

4 TRANSFER OF A SINGLE PCM OUTPUT

CHANNEL SAMPLE

5 TRANSFER OF A SINGLE OUTPUT

CHANNEL CONTROL WORD

6 TRANSFER OF A SELECTED 0 CHANNEL PCM

INPUT DATA ACCORDING TO AN 8-BIT MASK

PREVIOUSLY STORED IN THE ”EXPECTED

MESSAGES” REGISTER

The instruction flow is as follows.

Any input protocol is started by the microprocessor

interface loading the internal stack register with 2

bytes (4 bytes for instructions 1 and 3) qualified as

data bytes by C/D = 0 and a specific opcode quali-

fied by C/D = 1 (match condition is normally

needed).

After the code is loaded in the instruction register it

is immediately checked to see whether it is ac-

ceptable and if not it is rejected. If accepted the

instruction is also processed as regards match con-

dition and is appended for execution during the

memories’ spare cycles.

Four cases are possible :

a) the code is not valid ; executioncannot take place,

the DR output pin is reset to indicate the error ; all

registers are saved ;

b) the code is valid for types 2, 4 and 6 but it is un-

matched ; execution cannot take place, DR is not af-

fected.

c) the code is valid for types 1 and 3 and it is un-

matched ; the instruction is interpreted as a channel

disconnection.

d) the code is valid and is either matched or of type

5 ; the instruction is processed as received.

Validation control takes only two cycles out of a total

execution time of 4 to 7 cycles ; the last operation is

updating of the content of registers OR1 and OR2,

according to the following instruction tables.

M3488

12/18

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