PDSP16350

5

4) DC can be generated since the increment value can be

zero.

5) Frequency stability will match the stability of the incoming

frequency when the increment is fixed.

The residual noise characteristics of an oscillator are very

important in modern communication systems. This parameter

defines how well the device maintains its set frequency for

very short periods (nanoseconds to seconds) of time. Poor

figures will significantly affect the system signal to noise ratio

and limit the dynamic range.

The PDSP16350 will, of course, inherit the residual noise

characteristics of the source of the incoming frequency. The

output frequency is, however, always less than half the

incoming frequency in order to satisfy the Nyquist criterion.

This is in contrast to a phase locked loop synthesiser, when a

small input frequency controls a high output frequency.

The commonly used 20 log N rule states that the phase

noise at the output of a synthesiser will be no better than

twenty times the log of the ratio of the output frequency to the

input frequency. In a phase locked loop synthesiser N is large,

in the PDSP16350 it is less than half. Log N is thus less than

zero and phase noise improvement is obtained.

The output waveforms are produced after a pipeline delay

with respect to the DIN inputs. The effects of the JUMP or RES

commands are delayed such that all data in the internal pipe

will be processed before the discontinuity occurs. New data

may be presented to the device on the cycle following the

JUMP or RES and a valid result will be obtained after 31 clock

cycles.

DEVICE OPERATION

Sine and cosine are simultaneously produced by the

Cordic processor, which is addressed by the upper 16 bits of

the output from a 34 bit phase accumulator. The accumulator

divides the digital phase circle into a number of steps, one step

for each state of the accumulator. When the accumulator

reaches its maximum value it overflows back to zero and the

sequence is repeated.

The accumulator is incremented once per incoming clock

cycle, by an amount which defines the frequency which is to

be generated. The increment required is defined by :

Desired O/P Frequency

Increment =

Incoming Clock Frequency

where N is the number of bits in the accumulator. Since the

Nyquist criteria for proper waveform reconstruction must still

be obeyed, the maximum output frequency is half the incom-

ing frequency. In practice, when a return is made to the analog

world, just meeting the minimum Nyquist requirement would

require a ‘brick wall’ low pass filter to remove the alias signals.

A more useful ‘rule of thumb’ is to limit the generated wave-

forms to less than 40% of the clock frequency.

The resolution, or tuning sensitivity, of the waveform

generator is given by :

Incoming Clock Frequency

Resolution =

Hz

These equations illustrate some very important features of

direct digital synthesisers :-

1) Tuning sensitivity is defined by both the number of bits in

the accumulator and the incoming time base frequency.

2) The oscillator tunes linearly over its entire range.

3) The frequency accuracy matches the accuracy of the

incoming increment value.

1

2

3

4

5

CLK

RESET

DATA IN

RESULT

30

31

32

33

34

35

PI

PI

A

B

Device Reset

Apply phase increment

First Result Available

C

D

JUMP

MODE

CEN

Fig. 3 Fixed Frequency Timing Diagram