PDSP1601/PDSP1601A

10

INSTRUCTION SET

ALU Arithmetic Instructions

Function

On the rising edge of CLK at the end of the cycle in which this instruction is executing, the

A Port, B Port, ALU, Barrel Shifter, and Shift Control Registers will be loaded with zeros.

The internal registered CO will also be set to zero, and the BFP flag will be set to activate

on overflow conditions.

The A input to the ALU is inverted and a one is added to the LSB.

The A input to the ALU is inverted and the CI input is added to the LSB.

The A input to the ALU is inverted and the CO output from the ALU on the previous cycle

is added to the LSB.

The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant

MSB is filled by duplicating the original MSB (Sign Extension).

The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant

MSB is filled with the LSB from the ALU register.

The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant

MSB is filled with the LSB from the ALU register.

The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacant

MSB is filled with the LSB from the B input to the ALU.

The A input to the ALU is added to the B input, and the CI input is added to the LSB.

The A input to the ALU is added to the B input, and the CO out from the ALU on the previous

cycle is added to the LSB.

The A input to the ALU is added to the inverted B input, and a one is added to the LSB.

The A input to the ALU is added to the inverted B input, and the CI input is added to the

LSB.

The A input to the ALU is added to the inverted B input, and the CO out from the ALU on

the previous cycle is added to the LSB.

The inverted A input to the ALU is added to the B input, and a one is added to the LSB.

The inverted A input to the ALU is added to the B input, and the CI input is added to the

LSB.

The inverted A input to the ALU is added to the B input, and the CO out from the ALU on

the previous cycle is added to the LSB.

Op Code

<00>

<01>

<02>

<03>

<04>

<05>

<06>

<07>

<08>

<09>

<0A>

<0B>

<0C>

<0D>

<0E>

<0F>

Mnemonic

CLRXX

MIAX1

MIAC1

MIACO

A2SGN

A2RAL

A2RAR

A2RSX

APBCI

APBCO

AMBX1

AMBCI

AMBCO

BMAX1

BMAC1

BMACO

ALU Logical Instructions

Function

The A input to the ALU is logically 'ANDed' with the B input.

The A input to the ALU is logically 'ANDed' with the inverse of the B input.

The inverse of the A input to the ALU is logically 'ANDed' with the B input.

The A input to the ALU is logically 'ORed' with the B input.

The inverse A input to the ALU is logically 'ORed' with the B input.

The A input to the ALU is logically Exclusive-ORed with the B input.

The A input to the ALU is passed to the output.

The inverse of the A input to the ALU is passed to the output.

Op Code

<10>

<11>

<12>

<13>

<14>

<15>

<16>

<17>

Mnemonic

ANXAB

ANANB

ANNAB

ORXAB

ORNAB

XORAB

PASXA

PASNA