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36 Thornwood Dr. – Ithaca, NY 14850
© 2006 Kionix, Inc.
AN 009
Getting Started with the KXPS5
Introduction
This application note will help users quickly implement proof-of-concept designs using the I2C or
SPI digital interfaces of the KXPS5 tri-axis accelerometer. Please refer to the KXPS5 Data Sheet
for additional implementation guidelines.
Circuit Schematics
This section shows recommended wiring schematics for the KXPS5 when operating in both I2C
and SPI modes. It also describes an RC method for enabling the KXPS5 upon power up. Please
refer to the KXPS5 Data Sheet for all pin descriptions.
Note: these schematics are recommendations based on proven KXPS5 operation. Your specific
application may require modifications from these recommendations.
I
2C Schematic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Enable
X
Y
Z
FF/MOT
MOT Enable
C1
SCL
SDA
ADDR
KXPS5
Vdd
Vdd
Logic Input
Logic Output
Logic Input or RC
I2C
Vdd(1) or GND(0)
Master Clock
Bi-directional Data
R1
R2
GND
C4
C3
C2
R1, R2 = 2.1Kohm
Figure 1. Schematic for I2C Operation
tel: 607-257-1080 – fax: 607-257-1146
9 March 2006
www.kionix.com - info@kionix.com
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