M29F100T datasheet(13/30 Pages) STMICROELECTRONICS

13 / 30 page

Symbol

Parameter

Test Condition

Min

Max

Unit

ILI

Input Leakage Current

≤ VIN ≤ VCC

±1

µA

ILO

Output Leakage Current

≤ VOUT ≤ VCC

±1

µA

ICC1

Supply Current (Read) TTL Byte

E = VIL,G= VIH, f = 6MHz

ICC1

Supply Current (Read) TTL Word

E = VIL,G= VIH, f = 6MHz

ICC2

Supply Current (Standby) TTL

E = VIH

1mA

ICC3

Supply Current (Standby) CMOS

E = VCC

± 0.2V

100

µA

ICC4

(1)

Supply Current (Program or Erase)

Byte program, Block or

Chip Erase in progress

VIL

Input Low Voltage

–0.5

0.8

VIH

Input High Voltage

VCC + 0.5

VOL

Output Low Voltage

IOL = 5.8mA

0.45

VOH

Output High Voltage TTL

IOH = –2.5mA

2.4

Output High Voltage CMOS

IOH = –100

µAVCC –0.4V

VID

A9 Voltage (Electronic Signature)

11.0

12.0

IID

A9 Current (Electronic Signature)

A9 = VID

100

µA

VLKO

Supply Voltage (Erase and

Program lock-out)

3.2

4.2

Note: 1. Sampled only, not 100% tested.

Table 13. DC Characteristics

(TA = 0 to 70

°C, –40 to 85°C or –40 to 125°C; VCC =5V ± 10%)

During the executionof the erase by the P/E.C., the

memory accepts only the Erase Suspend ES and

Read/Reset RD instructions. Data Polling bit DQ7

returns ’0’ while the erasure is in progress and ’1’

when it has completed. The Toggle bit DQ2 and

DQ6 toggle during the erase operation. They stop

when erase is completed. After completion the

Status Register bit DQ5 returns ’1’ if there has been

an erase failure. In such a situation, the Toggle bit

DQ2 can be used to determine which block is not

correctly erased. In the case of erase failure, a

Read/Reset RD instruction is necessary in order to

reset the P/E.C.

Chip Erase (CE) Instruction. This instruction uses

six write cycles. The Erase Set-up command 80h

is written to address AAAAh in the Byte-wide con-

figuration or the address 5555h in the Word-wide

configuration on the third cycle after the two Coded

cycles. The Chip Erase Confirm command 10h is

similarly written on the sixth cycle after anothertwo

Coded cycles. If the second command given is not

an erase confirm or if the Coded cycles are wrong,

the instruction aborts and the device is reset to

Read Array. It is not necessaryto programthe array

with 00h first as the P/E.C. will automatically do this

before erasing it to FFh. Read operations after the

sixth rising edge of W or E output the Status

the P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’

on completion. The Toggle bits DQ2 and DQ6

toggle during erase operation and stop when erase

is completed. After completion the Status Register

bit DQ5 returns ’1’ if there has been an Erase

Failure.

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