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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STW81103AT датащи(PDF) 19 Page - STMicroelectronics |
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STW81103AT датащи(HTML) 19 Page - STMicroelectronics |
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19 / 53 page  STW81103 Circuit description 19/53 5 Circuit description 5.1 Reference input stage The reference input stage is shown in Figure 15. The resistor network feeds a DC bias at the Fref input, while the inverter used as the frequency reference buffer is AC coupled. Figure 15. Reference frequency input buffer 5.2 Reference divider The 10-bit programmable reference counter allows division of the input reference frequency to produce the input clock to the PFD. The division ratio is programmed through the digital interface. 5.3 Prescaler The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it down to a manageable frequency for the CMOS A and B counters. The modulus P is programmable and can be set to 16 or 19. The prescaler is based on a synchronous 4/5 core whose division ratio depends on the state of the modulus input. INV BUF VDD F ref Power Down |
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