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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7LITEU09 датащи(PDF) 36 Page - STMicroelectronics |
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ST7LITEU09 датащи(HTML) 36 Page - STMicroelectronics |
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36 / 115 page  ST7LITEU05 ST7LITEU09 36/115 SYSTEM INTEGRITY MANAGEMENT (Cont’d) Figure 21. Using the AVD to Monitor VDD 8.4.3 Low Power Modes 8.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is re- set (RIM instruction). VDD VIT+(AVD) VIT-(AVD) AVDF bit 01 RESET IF AVDIE bit = 1 Vhyst AVD INTERRUPT REQUEST INTERRUPT Cleared by VIT+(LVD) VIT-(LVD) LVD RESET Early Warning Interrupt (Power has dropped, MCU not not yet in reset) 0 1 hardware INTERRUPT Cleared by reset Mode Description WAIT No effect on SI. AVD interrupts cause the device to exit from Wait mode. HALT The SICSR register is frozen. The AVD remains active but the AVD inter- rupt cannot be used to exit from Halt mode. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No 1 |
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