TMS320DM641 datasheet(86/179 Pages) TI

86 / 179 page

Power Supplies

June 2003 − Revised October 2005

SPRS222E

Table 4−1. Board-Level Timing Example (see Figure 4−6)

NO.

DESCRIPTION

Clock route delay

Minimum DSP hold time

Minimum DSP setup time

External device hold time requirement

External device setup time requirement

Control signal route delay

External device hold time

External device access time

DSP hold time requirement

DSP setup time requirement

Data route delay

ECLKOUTx

(Output from DSP)

ECLKOUTx

(Input to External Device)

Control Signals†

(Output from DSP)

Control Signals

(Input to External Device)

Data Signals‡

(Output from External Device)

Data Signals‡

(Input to DSP)

† Control signals include data for Writes.

‡Data signals are generated during Reads from an external device.

Figure 4−6. Board-Level Input/Output Timings

4.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

4.3

Power Supplies

For more information regarding TI’s power management products and suggested devices to power TI DSPs,

visit www.ti.com/dsppower.

4.3.1

Power-Supply Sequencing

TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,

systems should be designed to ensure that neither supply is powered up for extended periods of time

(>1 second) if the other supply is below the proper operating voltage.

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