M25P10-A

18/41

Figure 12. Write Status Register (WRSR) Instruction Sequence

Table 7. Protection Modes

Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.

W

Signal

SRWD

Bit

Mode

Write Protection of the Status

Register

Memory Content

10

Software

Protected

(SPM)

Status Register is Writable (if the

WREN instruction has set the WEL

bit)

The values in the SRWD, BP1 and

BP0 bits can be changed

Protected against

Page Program, Sector

Erase and Bulk Erase

Ready to accept Page

Program and Sector

Erase instructions

00

11

01

Hardware

Protected

(HPM)

Status Register is Hardware write

protected

The values in the SRWD, BP1 and

BP0 bits cannot be changed

Protected against

Page Program, Sector

Erase and Bulk Erase

Ready to accept Page

Program and Sector

Erase instructions

C

D

AI02282D

S

Q

2

1

3456789 10 11 12 13 14 15

High Impedance

Instruction

Status

Register In

0

765432

0

1

MSB