M25P05-AV datasheet(17/34 Pages) STMICROELECTRONICS

17 / 34 page

17/34

M25P05-A

Figure 15. Sector Erase (SE) Instruction Sequence

Note: 1. Address bits A23 to A16 must be set to 00h.

Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh)

all bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction

must previously have been executed. After the

Write Enable (WREN) instruction has been decod-

ed, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, and three address bytes on Serial

Data Input (D). Any address inside the Sector (see

Table 3) is a valid address for the Sector Erase

(SE) instruction. Chip Select (S) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S) must be driven High after the

eighth bit of the last address byte has been latched

in, otherwise the Sector Erase (SE) instruction is

not executed. As soon as Chip Select (S) is driven

High, the self-timed Sector Erase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cy-

cle is in progress, the Status Register may be read

to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the

self-timed Sector Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL)

bit is reset.

A Sector Erase (SE) instruction applied to a page

which is protected by the Block Protect (BP1, BP0)

bits (see Tables 3 and 2) is not executed.

24 Bit Address

AI03751D

3456789

29 30 31

Instruction

23 22

MSB

M25P05-AV датащи(PDF) 17 Page - STMicroelectronics

M25P05-AV датащи(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

датащи скачать

ссылки URL