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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SMSXXXAF датащи(PDF) 28 Page - Numonyx B.V |
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SMSXXXAF датащи(HTML) 28 Page - Numonyx B.V |
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28 / 61 page  SD memory card hardware interface SMSxxxAF, SMSxxxFF, SMSxxxBF 28/61 4.3 Hot Insertion/Removal To guarantee a reliable initialization during hot insertion, some measures must be taken on by the host. For example, a special hot-insertion capable card connector may be used to guarantee the sequence of the card pin connection. The card contacts are connected in three steps: 1. Ground VSS (pin 3) and supply voltage VDD (pin 4). 2. CLK, CMD, DAT0, DAT1, DAT2 and VSS (pin 6). 3. CD / DAT3 (pin 1). Pins 3 and 4 should be connected first on insertion, and be disconnected last on extraction. Another method is a switch which could ensure that the power is switched on only after all card pads are connected. Inserting a Card in or removing it from the SD Memory Card bus with the power on will not damage the card. Data transfer operations are protected by CRC codes, therefore any bit changes induced by card insertion and removal can be detected by the SD Memory Card bus master. ● The inserted card must be properly reset even when the clock frequency is fPP. ● Each card should be fitted with a protection from the power supply to prevent damage to the card (and host). ● Data transfer failures induced by removal/insertion are detected by the bus master. They must be corrected by the application, which may repeat the issued command. 4.4 Power Protection Cards have to be inserted in or removed from the bus without being damaged. If one of the supply pins (VDD or VSS) is not connected properly, then the current is drawn through a data line. All the card outputs should also be able to withstand shortcuts to either supply. If the hot insertion feature is implemented in the host, then the host has to be able to withstand an instant shortcut between VDD and VSS without being damaged. 4.5 Electrical Specifications Table 16 defines the Bus Operating Conditions for the SD Memory Card. The total capacitance CL of the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus capacitance CBUS and the capacitances CCARD of all the cards connected to this line. CL = CHOST + CBUS + N × CCARD, where: ● N is the number of cards connected to the line. ● CHOST + CBUS must be lower than 30pF for up to 10 cards and lower than 40pF for up to 30 cards. ● The values in Table 16 should not be exceeded. As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. See Figure 15: Bus Signal levels and Table 17: Bus Signal Condition - I/O Signal Voltages. |
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