M58WR064HT datasheet(39/111 Pages) NUMONYX

39 / 111 page

M58WR064HT, M58WR064HB

Configuration Register

39/111

Configuration Register

The Configuration Register is used to configure the type of bus access that the memory will

perform. Refer to Read Modes section for details on read operations.

The Configuration Register is set through the Command Interface. After a Reset or Power-

Up the device is configured for asynchronous page read (CR15 = 1). The Configuration

type, burst X latency and the Read operation. Refer to Figures 5 and 6 for examples of

synchronous burst configurations.

8.1

Read Select Bit (CR15)

The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus

Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous;

when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst

Read is supported in both parameter and main blocks and can be performed across banks.

On reset or power-up the Read Select bit is set to’1’ for asynchronous access.

8.2

X-Latency Bits (CR13-CR11)

The X-Latency bits are used during Synchronous Read operations to set the number of

clock cycles between the address being latched and the first data becoming available. For

correct operation the X-Latency bits can only assume the values in Table 10: Configuration

Table 9shows how to set the X-Latency parameter, taking into account the speed class of

the device and the Frequency used to read the Flash memory in Synchronous mode.

8.3

Wait Polarity Bit (CR10)

In synchronous burst mode the Wait signal indicates whether the output data are valid or a

WAIT state must be inserted. The Wait Polarity bit is used to set the polarity of the Wait

signal. When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait

Polarity bit is set to ‘1’ the Wait signal is active High.

Table 9.

Latency Settings

fmax

tKmin

X-Latency (Min)

Speed 60ns

Speed 70ns

30MHz

33ns

40MHz

25ns

54MHz

19ns

66MHz

15ns

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