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M45PE40-VMP6TP датащи(PDF) 18 Page - Numonyx B.V

номер детали M45PE40-VMP6TP
подробное описание детали  4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte-alterability and a 50 MHz SPI bus interface
PDF  46 Pages
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производитель  NUMONYX [Numonyx B.V]
домашняя страница  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M45PE40-VMP6TP датащи(HTML) 18 Page - Numonyx B.V

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Instructions
M45PE40
18/46
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 6) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page
Program (PP), Page Erase (PE), and Sector Erase (SE) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 6.
Write Enable (WREN) instruction sequence
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 7) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
●
Power-up
●
Write Disable (WRDI) instruction completion
●
Page Write (PW) instruction completion
●
Page Program (PP) instruction completion
●
Page Erase (PE) instruction completion
●
Sector Erase (SE) instruction completion
Figure 7.
Write Disable (WRDI) instruction sequence
C
D
AI02281E
S
Q
2
1
34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
2
1
34567
High Impedance
0
Instruction



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