TP6312
1/4 TO 1/11-DUTY VFD CONTROLLER/DRIVER
Pin Configuration (Top View)
KEY 3
KEY 4
VDD
Seg1 / KS 1
Seg2 / KS 2
Seg3 / KS 3
Seg4 / KS 4
Seg5 / KS 5
Seg6 / KS 6
Se g7
Se g8
Grid 4
Grid 3
Grid 2
Grid 1
VDD
LED 4
LED 3
LED 2
LED 1
VS S
OS C
Use all the power pins.
Pin Description
Pin No
Symbol
Pin Name
Description
6
DIN
Date input
Inputs serial data at rising edge of shift clock,
starting from the lower bit.
5
DOUT
Date output
Outputs serial data at falling edge of shift clock,
starting from the lower bit.
This is N-ch open-drain
output pin.
9
STB
Strobe
Initializes the serial interface at rising or falling edge
to make TP6312 waiting for reception of command.
Data input after STB has fallen is processed as
command.
While command data is processed,
current processing is stopped and serial interface is
initialized.
While STB is high, CLK is ignored.
8
CLK
Clock input
Reads serial data at rising edge, and outputs data at
falling edge.
44
OSC
Oscillator pin
Connects a resistor to this pin to determine the
oscillation frequency to this pin.
15 to 20
Seg1/KS1 to
Seg6/KS6
High-voltage output
Segment output pins (Dual function as Key source).
21 to 25
Seg7 to Seg11
High-voltage output
(Segment)
Segment output pins.
37 to 32
Grid1 to Grid6
High-voltage output
(Grid)
Grid output pins.
26, 28 to 31
Seg11/Grid11 to
Seg16/Grid7
High-voltage output
(Segment/grid)
These pins are selectable for segment or grid
driving.
42 to 39
LED1 to LED4
LED output
CMOS output. +20 mA max.
10 to 13
Key1 to Key4
Key data input
Data input to these pins is latched at the end of
display cycle.
1 to 4
SW1 to SW4
Switch input
These pins constitute 4-bit general-purpose input
port.
14, 38
VDD
Logic power
5V ± 10%
7, 43
VSS
Logic ground
Connect this pin to system GND.
27
VEE
Pull-down level
VDD – 35 V max
Version 1.1
Page 2 of 9
http://www.topro.com.tw
September 2003
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
