6.42

7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

8

Feb.14.20

tRC

R/

W

CE

ADDR

tAA

(4)

OE

2738 drw 07

tACE

(4)

tAOE

(4)

tLZ

(1)

tOH

tHZ

(2)

tBDD

(3,4)

DATAOUT

BUSYOUT

VALID DATA

(4)

Waveform of Read Cycles(5)

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

2738 drw 08

tPU

ICC

ISB

tPD

,