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PIC16F15213 датащи(PDF) 103 Page - Microchip Technology |
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PIC16F15213 датащи(HTML) 103 Page - Microchip Technology |
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103 / 408 page ![]() 15.1.1.2 Self-Programming The program memory cell and control logic will support write and row erase operations across the entire VDD range. Bulk Erase is not available when self-programming. 15.2 FSR and INDF Access The FSR and INDF registers allow indirect access to the Program Flash Memory. 15.2.1 FSR Read With the intended address loaded into an FSR register a MOVIW instruction or read of INDF will read data from the program memory. Reading from NVM requires one instruction cycle. The CPU operation is suspended during the read, and resumes immediately after. Read operations return a single byte of memory. 15.2.2 FSR Write Writing/erasing the NVM through the FSR registers (ex. MOVWI instruction) is not supported in the PIC16F152 devices. 15.3 NVMREG Access The NVMREG interface allows read/write access to all the locations accessible by FSRs, read/write access to the User ID locations, and read-only access to the device identification, revision, and configuration data. Writing or erasing of NVM via the NVMREG interface is prevented when the device is write-protected. 15.3.1 NVMREG Read Operation To read a NVM location using the NVMREG interface, the user must: 1. Clear the NVMREGS bit if the user intends to access program memory locations, or set NMVREGS if the user intends to access User ID or configuration locations. 2. Write the desired address into the NVMADRH:NVMADRL register pair. 3. Set the RD bit to initiate the read. Once the read control bit is set, the CPU operation is suspended during the read, and resumes immediately after. The data is available in the very next cycle, in the NVMDATH:NVMDATL register pair; therefore, it can be read as two bytes in the following instructions. NVMDATH:NVMDATL register pair will hold this value until another read or until it is written to by the user. Upon completion, the RD bit is cleared by hardware. PIC16F15225/45 NVM - Nonvolatile Memory Control © 2020 Microchip Technology Inc. Preliminary Datasheet DS20006389B-page 103 |
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