PIC16F15213 datasheet(84/408 Pages) MICROCHIP

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The following events happen when an interrupt event occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the stack

• Critical registers are automatically saved to the shadow registers (see “Automatic Context Saving”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the

interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because

the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but

will not cause the processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context

from the shadow registers and setting the GIE bit.

For additional information on a specific interrupts operation, refer to its peripheral chapter.

Important:

Individual interrupt flag bits are set, regardless of the state of any other enable bits.

All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is

clear will be serviced when the GIE bit is set again.

12.5

Interrupt Latency

Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the

interrupt vector begins. The interrupt is sampled during Q1 of the instruction cycle. The actual interrupt latency then

depends on the instruction that is executing at the time the interrupt is detected. See the following figures for more

details.

Figure 12-2. Interrupt Latency

Filename:

10-000269E.vsd

Title:

INT LATENCY - ONE CYCLE

Last Edit:

8/31/2016

First Used:

PIC16(L)F18325/45 (MFAH)

Notes:

Rev. 10-000269E

8/31/2016

OSC1

CLKOUT

INT

PC - 1

Fetch

Execute

PC - 2

PC - 1

PC + 1

NOP

PC = 0x0004

PC = 0x0005

PC = 0x0006

1 Cycle Instruction at PC

Latency

Valid Interrupt

window

(1)

Indeterminate

Latency

(2)

Note 1: An interrupt may occur at any time during the interrupt window.

2: Since an interrupt may occur any time during the interrupt window, the actual latency can vary.

PIC16F15225/45

Interrupts

Preliminary Datasheet

DS20006389B-page 84

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