Preliminary Data Sheet #: SG040
Page 2 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Absolute Maximum Rating
Table 1
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
V
cc
Power Supply Voltage
-0.5
-
+4.0
Volts
1.0
V
i
Input Voltage
-0.5
-
+5.5
Volts
1.0
T
s
Storage Temperature
-65.0
-
+100
°C
1.0
General Description
The SCG4501 is a mixed-signal phase locked loop
generating LVPECL outputs from an intrinsically low
jitter, voltage controlled, crystal oscillator. The LVPECL
outputs may be disabled.
The SCG4501 can lock to one of two external
references, which is selectable using the SEL
AB input
select pin. The unit has a fast acquisition time of about
1.5 seconds and it is tolerant of different reference duty
cycles.
The SCG4501 includes an alarm output that
indicates deviations from normal operation. If a Loss-
of-Reference (LOR) or Loss-of-Lock (LOL) is detected
the alarm with indicate the need for a reference
rearrangement. If both references A and B are absent
the module will enter Free Run operation. The FR
status
pin will indicate that the module is in Free Run
operation. Frequency stability during Free Run
operation is guaranteed to ±20 ppm. Additionally the
Free Run mode may be entered manually.
The package dimensions are 1” x 1.025” x .45” on a
6 layer FR4 board with castellated pins. Parts are
assembled using high temperature solder to withstand
63/37 alloys, 180°C surface mount reflow processes.
Maximum Dimension Package Outline
Figure 1
Block Diagram
Figure 2
8 KHz PHASE
ALIGNER
REFB
REFA
SEL AB
ANALOG
FILTER
Q
QN
1 / N
ALARM
LOW JITTER
VCXO
FREE RUN STATUS
OPTIONAL
REFERENCE
OUTPUT
FORCE
FREE RUN
ENABLE/
TRI-STATE
33
Ω
10 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
33
Ω
33
Ω
DPFD
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