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PRELIMINARY
W150
Document #: 38-07177 Rev. *B
Page 7 of 15
4
14
PCI4
Clock Output Disable
Low
Active
1
3
13
PCI3
Clock Output Disable
Low
Active
1
2
12
PCI2
Clock Output Disable
Low
Active
1
1
11
PCI1
Clock Output Disable
Low
Active
1
0
9
PCI0
Clock Output Disable
Low
Active
1
Data Byte 3
7
––
(Reserved)
––
0
6
––
(Reserved)
––
0
5
29
48MHz
Clock Output Disable
Low
Active
1
4
30
24MHz
Clock Output Disable
Low
Active
1
3
33, 32,
25, 24
SDRAM12:15 Clock Output Disable
Low
Active
1
2
22, 21,
19, 18
SDRAM8:11
Clock Output Disable
Low
Active
1
1
39, 38,
36, 35
SDRAM4:7
Clock Output Disable
Low
Active
1
0
44, 43,
41, 40
SDRAM0:3
Clock Output Disable
Low
Active
1
Data Byte 4
7
––
(Reserved)
––
0
6
––
(Reserved)
––
0
5
––
(Reserved)
––
0
4
––
(Reserved)
––
0
3
––
(Reserved)
––
0
2
––
(Reserved)
––
0
1
––
(Reserved)
––
0
0
––
(Reserved)
––
0
Data Byte 5
7
––
(Reserved)
––
0
6
––
(Reserved)
––
0
5
54
IOAPIC_F
Disabled
Low
Active
1
4
55
IOAPICO
Disabled
Low
Active
1
3
––
(Reserved)
––
0
2
––
(Reserved)
––
0
1
2
REF1
Clock Output Disable
Low
Active
1
0
3
REF0
Clock Output Disable
Low
Active
1
Table 5. Data Bytes 0–5 Serial Configuration Map (continued)
Bit(s)
Affected Pin
Control Function
Bit Control
Default
Pin No.
Pin Name
0
1
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