W144
Document #: 38-07153 Rev. *B
Page 12 of 14
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.6/100.2 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.31818
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
1
–
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
–
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.25V
45
–
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
––
1.5
ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
–15–
Ω
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.6/100.2 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
–
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
–
2V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
––
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
–40–
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
CPU = 66.6/100.2 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Determined by PLL divider ratio (see p/q below)
–48.008–
MHz
fD
Deviation from 48 MHz (48.008 – 48)/48
+167
ppm
p/q
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
–57/17
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
0.5
–
2
V/ns
tF
Output Fall Edge Rate Measured from 2.4V to 0.4V
0.5
–
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
––3
ms
Zo
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
–40–
Ω
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz
Parameter
Description
Test Condition/Comments
CPU = 66.6/100.2 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Determined by PLL divider ratio (see p/q below)
24.004
MHz
fD
Deviation from 24 MHz (24.004 – 24)/24
+167
ppm
p/q
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
57/34
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
0.5
–
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
–
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
