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TMP512 датащи(PDF) 40 Page - Texas Instruments |
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TMP512 датащи(HTML) 40 Page - Texas Instruments |
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40 / 63 page ![]() 8.23 Alert_Mask Register (Address = 1Fh) [reset = 00h] This register controls whether either of remote channel or the local channel is masked. Masking an alert prevents the ALERT pin from being asserted low in Interrupt Mode. Return to Register Map. Figure 8-23. Alert_Mask Register 7 6 5 4 3 2 1 0 Reserved Mask_Ch2 Mask_Ch1 Mask_L R-00h R/W-0h R/W-0h R/W-0h Table 8-25. Alert_Mask Register Field Descriptions Bit Field Type Reset Description 7:3 Reserved R 00h Reserved 2 Mask_Ch2 R/W 0h Setting this bit to 1 prevents the ALERT pin from being asserted low when remote channel 2 is out of the temperature limit or encounters a diode fault condition. 1 Mask_Ch1 R/W 0h Setting this bit to 1 prevents the ALERT pin from being asserted low when remote channel 1 is out of the temperature limit or encounters a diode fault condition. 0 Mask_L R/W 0h Setting this bit to 1 prevents the ALERT pin from being asserted low when the local channel is out of the temperature limit. TMP4719 SBOSAJ7A – OCTOBER 2025 – REVISED DECEMBER 2025 www.ti.com 40 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TMP4719 |
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