CY29653
Document #: 38-07477 Rev. *C
Page 2 of 7
Pin Description[1]
Pin
Name
I/O
Type
Description
8
PECL_CLK
I, PU
LVPECL
LVPECL reference clock input
9
PECL_CLK#
I, PU
LVPECL
LVPECL reference clock input. Pull-up to VDD/2.
12, 14, 16,
18, 20, 22,
24, 26
Q(7:0)
O
LVCMOS
Clock output
28
FB_OUT
O
LVCMOS
Feedback clock output. Connect to FB_IN for normal operation.
2
FB_IN
I, PU
LVCMOS
Feedback clock input. Connect to FB_OUT for normal operation. This
input should be at the same voltage rail as input reference clock. See
Frequency Table.
10
MR/OE#
I, PD
LVCMOS
Output enable/disable input. See Function Table.
30
PLL_EN
I, PU
LVCMOS
PLL enable/disable input. See Function Table.
31
BYPASS#
I, PU
LVCMOS
PLL and output divider bypass select input. See Function Table.
32
VCO_SEL
I, PU
LVCMOS
VCO divider select input. See Function Table.
11, 15, 19, 23 VDDQ
Supply
VDD
3.3V Power supply for output clocks[2]
1
AVDD
Supply
VDD
3.3V Power supply for PLL[2]
27
VDD
Supply
VDD
3.3V Power supply for core and inputs[2]
7
AVSS
Supply
Ground
Analog Ground
13, 17, 21,
25, 29
VSS
Supply
Ground
Common Ground
3, 4, 5, 6
NC
No connection
Frequency Table
Feedback Output Divider
VCO
Input Frequency Range
÷4
Input Clock * 4
35 MHz to 125 MHz
÷8
Input Clock * 8
25 MHz to 62.5 MHz
Function Table
Control
Default
0
1
VCO_SEL
1
VCO
÷ 1VCO ÷ 2
PLL_EN
1
Bypass mode, PLL disabled. The input
clock connects to the output dividers
PLL enabled. The VCO output connects to the
output dividers
BYPASS#
1
Bypass mode with PLL and output
dividers bypassed. The input clock
connects to the outputs.
Selects the output dividers
MR/OE#
0
Outputs enabled
Outputs disabled (three-state), VCO running at
its minimum frequency
Notes:
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1-
µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
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