CY29658
Document #: 38-07478 Rev. **
Page 2 of 7
Pin Description[1]
Pin
Name
I/O
Type
Description
6
PECL_CLK
I, PU
LVPECL
LVPECL reference clock input.
7
PECL_CLK#
I, PU
LVPECL
LVPECL reference clock input. Pull-up to VDD/2.
10, 12, 14,
16, 18, 20,
22, 24, 26, 28
Q(9:0)
O
LVCMOS
Clock output.
30
FB_OUT
O
LVCMOS
Feedback clock output. Connect to FB_IN for normal operation.
2
FB_IN
I, PU
LVCMOS
Feedback clock input. Connect to FB_OUT for normal operation. This
input should be at the same voltage rail as input reference clock. See
Table 1.
5MR/OE#
I, PD
LVCMOS
Output enable/disable input. See Table 2.
4
PLL_EN
I, PU
LVCMOS
PLL enable/disable input. See Table 2.
3
BYPASS#
I, PU
LVCMOS
PLL and output divider bypass select input. See Table 2.
32
VCO_SEL
I, PU
LVCMOS
VCO divider select input. See Table 2.
11, 15, 19,
23, 31
VDDQ
Supply
VDD
2.5V or 3.3V power supply for output clocks.[2,3]
1
AVDD
Supply
VDD
2.5V or 3.3V power supply for PLL.[2,3]
27
VDD
Supply
VDD
2.5V or 3.3V power supply for core and inputs.[2,3]
8
AVSS
Supply
Ground
Analog ground.
9, 13, 17, 21,
25, 29
VSS
Supply
Ground
Common ground.
Table 1. Frequency Table
Feedback Output Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
÷2
Input Clock * 2
100 MHz to 200 MHz
100 MHz to 200 MHz
÷4
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 100 MHz
Table 2. Function Table
Control
Default
0
1
VCO_SEL
1
VCO
÷ 1VCO ÷ 2
PLL_EN
1
Bypass mode, PLL disabled. The input
clock connects to the output dividers
PLL enabled. The VCO output connects to the
output dividers
BYPASS#
1
Bypass mode with PLL and output
dividers bypassed. The input clock
connects to the outputs.
Selects the output dividers
MR/OE#
0
Outputs enabled
Outputs disabled (three-state), VCO running at
its minimum frequency
Notes:
1.
PU = Internal pull-up, PD = Internal pull-down.
2.
A 0.1-
µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.
AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQ power supply pin.
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