CY28443ZXC datasheet(9/25 Pages) CYPRESS

9 / 25 page

PRELIMINARY

CY28443

Document #: 38-07716 Rev *C

Page 9 of 25

RESERVED

RESERVED, Set = 1

PCIF0

33-MHz Output Drive Strength

0 = Low, 1 = High

Byte 8: Control Register 8 (continued)

Bit

@Pup

Name

Description

Byte 9: Control Register 9

Bit

@Pup

Name

Description

27_96_100_SSC Spread Spectrum Selection table:

S[3:0] SS%

‘0000’ = –0.5%(Default value)

‘0001’ = –1.0%

‘0010’ = –1.5%

‘0011’ = –2.0%

‘0100’ = ±0.25%

‘0101’ = ±0.5%

‘0110’ = ±0.75%

‘0111’ = ±1.0%

‘1000’ = –0.35%

‘1001’ = –0.68%

‘1010’ = –1.09%

‘1011’ = –1.425%

‘1100’ = ±0.17%

‘1101’ = ±0.34%

‘1110’ = ±0.545%

‘1111’ = ±0.712%

RESERVED

RESERVED, Set = 1

27M Spread

27-MHz Spread Output Enable

0 = Disable (Hi-Z), 1 = Enable

27M_SS/LCD100M

Spread Enable

27M_SS/LCD100M Spread spectrum enable.

0 = Disable, 1 = Enable.

PCIF1

33-MHz Output Drive Strength

0 = Low, 1 = High

Byte 10: Control Register 10

Bit

@Pup

Name

Description

SRC[T/C]11

SRC[T/C]11 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]9

SRC[T/C]9 Output Enable

0 = Disable (Hi-Z), 1 = Enable

RESERVED

RESERVED, Set = 1

SRC[T/C]8

SRC[T/C]8 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]9

Allow control of SRC[T/C]9 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

SRC[T/C]11

Allow control of SRC[T/C]11 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

RESERVED

RESERVED, Set = 0

SRC[T/C]8

Allow control of SRC[T/C]8 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

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