6

FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED

SEQUENTIAL LOGIC CIRCUITS

Timing Diagrams

FIGURE 4.

FIGURE 5.

GND

GND

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

50%

50%

90%

10%

50%

90%

IC

50pF

P

N

P

N

PN

P

N

D

Q

C

FF DETAIL

Q

R

CLOCK

MASTER

RESET

CLOCK

ENABLE

“0”

“1”

“2”

“3”

“4”

“5”

“6”

“7”

“8”

“9”

TERMINAL

COUNT

0

1

2

3

4

5

6

7

8

9

0

1

2

CD54HC4017, CD74HC4017