DS14285/DS14287

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Table 2. Periodic Interrupt Rate and Square-Wave Output Frequency

SELECT BITS REGISTER A

RS3

RS2

RS1

RS0

INTERRUPT RATE

SQW OUTPUT

FREQUENCY

0

0

0

0

None

None

0

0

0

1

3.90625ms

256Hz

0

0

1

0

7.8125ms

128Hz

0

0

1

1

122.070

µs

8.192kHz

0

1

0

0

244.141

µs

4.096kHz

0

1

0

1

488.281

µs

2.048kHz

0

1

1

0

976.5625

µs

1.024kHz

0

1

1

1

1.953125ms

512Hz

1

0

0

0

3.90625ms

256Hz

1

0

0

1

7.8125ms

128Hz

1

0

1

0

15.625ms

64Hz

1

0

1

1

31.25ms

32Hz

1

1

0

0

62.5ms

16Hz

1

1

0

1

125ms

8Hz

1

1

1

0

250ms

4Hz

1

1

1

1

500ms

2Hz

UPDATE CYCLE

The DS14285/DS14287 executes an update cycle once per second regardless of the SET bit in Register B.

When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and

alarm bytes is frozen and will not update as the time increments. However, the time countdown chain

continues to update the internal copy of the buffer. This feature allows time to maintain accuracy

independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and

calendar information is consistent. The update cycle also compares each alarm byte with the

corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three

positions.

There are three methods that can handle access of the real-time clock that avoid any possibility of

accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If

enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read

valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared

before leaving the interrupt routine.

A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in

progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs

244

µs later. If a low is read on the UIP bit, the user has at least 244 µs before the time/calendar data will

be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed

to read valid time/calendar data to exceed 244

µs.

The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in

Register A is set high between the setting of the PF bit in Register C (see Figure 4). Periodic interrupts

data is not read during the update cycle.