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CY7C024/0241
CY7C025/0251
Document #: 38-06035 Rev. *C
Page 13 of 21
Notes:
36. CE = HIGH for the duration of the above timing (both write and read cycle).
37. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
38. Semaphores are reset (available to both ports) at cycle start.
39. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Switching Waveforms (continued)
tSOP
tAA
VALID ADRESS
VALID ADRESS
tHD
DATAIN VALID
DATAOUT VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA
tPWE
tSWRD
tDOE
WRITE CYCLE
READ CYCLE
OE
R/W
I/O 0
SEM
A 0–A 2
Semaphore Read After Write Timing, Either Side[36]
MATCH
tSPS
A0L–A2L
MATCH
R/WL
SEML
A0R–A2R
R/WR
SEM R
Timing Diagram of Semaphore Contention[37, 38, 39]
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