CY2V9950
Document #: 38-07436 Rev. *A
Page 2 of 9
Device Configuration
The outputs of the CY2V9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 1 and 2 respectively.
The divider settings, output frequencies, and possible config-
urations of connecting FB to ANY output are summarized in
Table 3.
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY2V9950 PLL operating frequency range that
corresponds to each FS level is given in Table 4.
Notes:
1.
‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up. ‘3’ indicates a three-level input buffer.
2.
A bypass capacitor (0.1
µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
3.
When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. The 1F[0:1]
and 2F[0:1] pins should be either tied to mid-level or left floating (on-chip resistors will bias to mid-level) during normal operation.
4.
LL disables outputs if TEST = MID and sOE# = HIGH.
5.
When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH, sOE# disables them LOW when PE = LOW.
6.
These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency at a given
reference frequency (FREF) and divider and feedback configurations. The user must select a configuration and a reference frequency that will generate a VCO
frequency that is within the range specified by FS pin. Refer to Table 4.
Pin Definitions
Pin
Name
I/O[1]
Type
Description
29
REF
I
LVTTL/LVCMOS
Reference Clock Input.
13
FB
I
LVTTL
Feedback Input.
27
TEST
I
3-Level
When MID or HIGH, disables PLL (except for conditions of note 3).
REF goes to all outputs. Set LOW for normal operation.
22
sOE#
I, PD
2-Level
Synchronous Output Enable. When HIGH, it stops clock outputs (except
2Q0 and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be
used as the feedback signal to maintain phase lock. When TEST is held at
MID level and sOE# is high, the nF[1:0] pins act as output disable controls
for individual banks when nF[1:0] = LL. Set sOE# LOW for normal
operation.
4PE
I, PU
LVTTL
Selects Positive or Negative Edge Control and High or Low output
drive strength. When LOW / HIGH the outputs are synchronized with the
negative/positive edge of the reference clock. Please see Table 5.
24, 23, 26,
25, 1, 32, 3, 2
nF[1:0]
I
3-Level
Select frequency of the outputs. Please see Tables 1 and 2.
31
FS
I
3-Level
Selects VCO operating frequency range. Please see Table 4.
19, 20, 15,
16,10,11, 6,
7
nQ[1:0]
O
LVTTL
Four banks of two outputs. Please see Tables 1 and 2 for frequency
settings.
21
VDDQ1[2] PWR Power
Power supply for Bank 1 and Bank 2 output buffers. Please see Table 6
for supply level constraints
12
VDDQ3[2]
PWR
Power
Power supply for Bank 3 output buffers. Please see Table 6 for supply
level constraints
5
VDDQ4[2] PWR Power
Power supply for Bank 4 output buffers. Please see Table 6 for supply
level constraints
14,30
VDD[2]
PWR Power
Power supply for internal circuitry. Please see Table 6 for supply level
constraints
8, 9, 17, 18,
28
VSS
PWR
Power
Ground.
Table 1. Output Divider Settings – Bank 3
3F[1:0]
K – Bank3 Output Divider
LL[4]
2
HH
4
Other
1
Table 2. Output Divider Settings – Bank 4
4F[1:0]
M – Bank4 Output Divider
LL[4]
2
HH
Inverted[5]
Other
1
Table 3. Output Frequency Settings
Configuration
Output Frequency
FB to
1Q, 2Q [6]
3Q
4Q
1Qn, 2Qn
FREF
(1/K) x FREF
(1/M) x FREF
3Qn
K x FREF
FREF
(K/M) x FREF
4Qn
M x FREF
(M/K) x FREF
FREF
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