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CY2SSTV8575
Document #: 38-07458 Rev. **
Page 6 of 8
Notes:
5.
Parameters are guaranteed by design and characterization. Not 100% tested in production.
6.
PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 50 kHz with a down
spread of –0.5%.
7.
While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC,
where the cycle time (tC) decreases as the frequency goes up.
8.
Refers to transition of non-inverting output.
9.
All differential input and output terminals are terminated with 120
Ω/16 pF as shown in Figure 2.
AC Input Parameters (AVDD = VDDQ = 2.5 ±5%, TA = 0°C to +85°C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fin
Input Frequency
1.25
60
–
170
MHz
DTYC
Input Duty Cycle
AVDD, VDD = 2.5V±0.2V
40
–
60
%
AC Output Parameters (AVDD= VDDQ = 2.5 ±5%, Temperature = 0°C to +85°C)[5,6]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
FOR
Output frequency range
AVDD, VDD = 2.5V±0.2V
60
–
170
MHz
tLOCK
Maximum PLL Lock Time
AVDD, VDD = 2.5V±0.2V
––
100
µS
DTYC
Duty Cycle[7]
60 MHz to 100 MHz
49.5
50
50.5
%
101 MHz to 170 MHz
49
–
51
%
TR
Rise Time
20% to 80% of VOD
1
–
2V/ns
TF
Fall Time
20% to 80% of VOD
1
–
2V/ns
tSKEW
Any Output to Any Output Skew[9]
All outputs equally loaded
––
100
ps
TPLH
Propagation Delay (Low to High)
CLK to Y
1.5
3.5
6
ns
TPHL
Propagation Delay (High to Low)
CLK to Y
1.5
3.5
6
ns
TODIS
Output Disable Time[8]
All outputs
–
3
–
ns
TOENB
Output Enable Time[8]
All outputs
–
3
–
ns
TJIT(CC)
Cycle to Cycle Jitter
All outputs @ 66 MHz
–100
––100
ps
TPHASE
Phase Error
–150
–
150
ps
TJIT(PHASE) Phase Error Jitter
All outputs @ 66 MHz
–50
–
50
ps
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