Frequency Synchronization

(Continued)

over/undershoot. Note that sharp edged signals from a pulse

or function generator can develop under/overshoot as high

as 10V at the end of an improperly terminated cable.

Over-voltage Protection

The LM3661 has an over-voltage comparator that prevents

the output voltage from rising too high when the device is left

in PWM mode under low-load conditions. Otherwise, the

output voltage could rise out of regulation from the minimum

energy transferred per cycle due to about 250 ns minimum

on-time of the PFET switch while in PWM mode. When the

output voltage rises by 70 mV over its regulation threshold,

the OVP comparator inhibits PWM operation to skip pulses

until the output voltage returns to the regulation threshold. In

over voltage protection, output voltage and ripple increase

slightly.

Shutdown Mode

Setting the EN input low, to SGND, places the LM3661 in a

0.5 µA (typ) shutdown mode. During shutdown, the PFET

switch, NFET synchronous rectifier, reference, control and

bias of the LM3661 are turned off. Setting EN high to V

DD

enables normal operation. While turning on, soft start is

activated. EN is a Schmidt trigger digital input with thresh-

olds that are independent of the input voltage at V

must be set low to turn off the LM3661 during under voltage

conditions when the supply is less than the 2.7V minimum

operating voltage. The LM3661 is designed for mobile

phones and similar applications where power sequencing is

determined by the system controller and internal UVLO (Un-

der Voltage Lock Out) circuitry is unnecessary. The LM3661

has no UVLO circuitry. Although the LM3661 exhibits good

behavior while enabled at low input voltages, this is not

guaranteed.

Start-up

The LM3661 is designed to be started in LDO mode. Under

these conditions, the output voltage will increase at a rate

determined by the LDO current limit and the output capacitor

and load. This ramp time is typically about 600 µs. The

LM3661 may be started in PWM mode as well. Under these

conditions, the reference voltage for the error amplifier is

ramped up time is about 300µs and the output voltage will

follow. In this way, the input inrush current and output voltage

over shoot can be minimized.

Thermal Shutdown Protection

The LM3661 has thermal shutdown protection in PWM mode

to protect from short-term misuse and overload conditions.

When the junction temperature exceeds 150˚C, the device

shuts down and re-starts in soft start after the temperature

drops below 130˚C. Prolonged operation in thermal overload

conditions may damage the device and is considered bad

practice.

Current Limiting Protection

A current limit feature allows the LM3661 to protect itself and

external components during overload conditions. Current

limiting is implemented using an independent internal com-

parator. In PWM mode, cycle-by-cycle current limiting is

normally used. If an excessive load pulls the output voltage

down to approximately 0.45V, then the device switches to a

timed current limit mode. In timed current limit mode the

internal PFET switch is turned off after the current compara-

tor trips and the beginning of the next cycle is inhibited for

2.5 µs to force the instantaneous inductor current to ramp

down to a safe value. Timed current limit prevents the loss of

current control seen in some products when the output volt-

age is pulled low in serious overload conditions.

Application Information

PIN SELECTABLE OUTPUT

The LM3661 features pin-selectable output voltage to elimi-

nate the need for external feedback resistors. Select an

output voltage of 1.05V or 1.25V/1.35V/1.4V by setting the

V

V

driven off digitally by a logic gates that provide over 1.2V for

high state and less than 0.4V for a low state to ensure valid

logic levels. V

the input low, this pin must be set to a known state.

Isel Pin

Connecting the I

to high value. Note that I

and this pin must connect to a known state of normal opera-

tion.

Table 1 shows selected I

Table 1. I

(Applies to both V

V

I

SEL

I

1.05V/1.25V

H

300mA

1.05V/1.25V

L

TBDmA

1.05V/1.35V

H

350mA

1.05V/1.35V

L

450mA

1.05V/1.40V

H

350mA

1.05V/1.40V

L

450mA

Mode Transition

The LM3661 is designed to operate in two modes, LDO(Low

Dropout Regulator) mode for light load (15mA Max.) and

PWM Mode (Pulse Width Modulation) . As described in the

Device Operation Section, setting the SYNC/MODE pin low

yields LDO mode or high yields PWM mode. When mode

transitions from LDO to PWM and vice versa, harsh transient

conditions such as ramping the output load should be

avoided. To maintain a smooth transition, it is recommended

to keep the load to a minimum of 3mA or less for about 40us

before ramping into heavy load to avoid a large dip at the

output. Similarly, the same care must be applied when

changing output voltage from 1.05V to 1.25V/1.35V/1.40V

and vice versa (setting Vsel pin high or low) during full load.

Figure 3 below shows the mode transition from LDO to PWM

and PWM to LDO, and the load transient transition from light

load to heavy load is delayed by 40µs to allow the PWM loop

to respond properly.

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