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Short-Circuit and Overtemperature Protection (SCB)

If the output current increases above the short current limit for a longer time than t_SCB or if the temperature

control signal at the NON-Input is switched off and on again. This filter time has the purpose to suppress wrong

detection on short spikes.

All four outputs have an independent overtemperature detection and shutdown. This measurement is active

while the powerstage is switched on.

The Short circuit detection and the overtemperature detection are using the same bit in the Diagnostic (one for

each channel).

A SCG failure will be recognized, when the drain voltage of the output stage is lower as the “Short Cut to Ground

threshold voltage”, while the output stage is switched off (see Fig. 4). The SCG failure is filtered with a digital

filter (t_SCG) to suppress the storage of a failure at small SCG spikes, which are typical during the transition of

the power output. This filter is triggered by the NON input and the (analog) SCG detection.

If the current through the output stage is lower than the IOL-reference, then an OL failure will be recognized

after a filter time. This measurement is active while the powerstage is switched on.

The Open Load failure detection has 2 different modes, the statical failure detection and the sporadic failure

detection. One main difference is, that a statical failure is transferred to the Failure register with the next rising

edge of NON, whereas a sporadic failure is transferred immediately to the Failure register (see fig. 5, 6 and 7).

same digital filter for suppression of spikes.

The failures are stored regarding to their priority (see above). A failure with a higher priority overwrites an even-

tually already detected failure with a lower priority.

Diagnostic interface

The communication between the microprocessor and the failure register runs via the SPI link. If there is a failure

stored in the failure register, the first bit of the shift register is set to a high level. With the H/L change at the NCS

pin the first bit of the diagnostic shift register will be transmitted to the SDO output. The SDO output is the serial

output from the diagnostic shift register and it is tristate when the NCS pin is high. The CLK pin clocks the diag-

nostic shift register. New SDO data will appear on every rising edge of the CLK pin and new SDI data will be

latched on every falling edge into the shift register. With the first positive pulse of the CLK the contents of the

failure register is copied to the SPI shift register and a internal reset (FR_RESET) is generated. This internal

reset clears the failure register and thus the failure register is capable of detecting failures also during the SPI

read cycle. There is no bus collision at a small spike at the NCS. The CLK has to be LOW, while the NCS signal

is changing.

Current feedback

Each channel has a current feedback output which sinks a current proportional to the load current of the Low

Side Switch. Using this output servo loop applications can be realized by applying a PWM signal to the NON

input. A typical diagram of the Current Feedback output at different temperatures is shown in figure 9.