LAN8808DSLASHKDX datasheet(52/80 Pages) MICROCHIP

52 / 80 page

LAN8808D

DS00005833C-page 52

The device’s PLL is normally enabled during EDPD. It can be set to be disabled during EDPD by setting the DGT_ed-

pd_pll_dis bit in MMD31 Register 19.

Normally, previous register setting are maintained when EDPD mode is cleared. With the PLL disabled, a device reset

occurs following the removal of EDPD (or if the DGT_edpd_pll_dis bit is cleared during EDPD), in which case register

settings will return to their defaults.

5.18.3

SOFTWARE POWER-DOWN MODE

The device supports a Software Power-Down (SPD) mode. This mode is used to power down the device when it is not

in use after power-up. SPD mode is enabled by writing a one to the Power Down bit in the Basic Control register. The

device may also be placed into software power-down by default by setting the MODE_SEL[4:0] configuration straps to

‘0100x’. The device exits the SPD state after a zero is written to the Power Down bit.

Previous register settings are maintained during and following the removal of SPD.

The following remain operational during SPD:

• MII Management Interface

- Only access to the standard registers (0 through 31) is supported.

- Access to MMD address spaces other than MMD Address Space 1 is possible if the spd_clock_gate_override

bit is set.

- Access to MMD Address Space 1 is not possible.

•PLL

- Normally the PLL is enabled during SPD. It may be disabled by setting the spd_pll_disable bit described

below.

• Bandgap

- This is always enabled.

• Internal Slow Oscillator

- This is always enabled.

The following are normally disabled during SPD:

• ADC/PGA/TX/common bias circuits

•DLL

• TX and RX clocks

- If the above mentioned spd_clock_gate_override bit is set, TX and RX clocks would be enabled. They may

alternately be stopped by setting the Isolate (PHY_ISO) bit in the Basic Control register.

5.18.3.1

SPD Extra Power Savings

To achieve a lower power usage, the PLL may be disabled during SPD mode by setting the spd_pll_disable bit in the

Digital Debug Control 2 register prior to entering SPD. The device may also be placed into software power-down with

the PLL disabled by default by setting the MODE_SEL[4:0] configuration straps to ‘01001’.

With the PLL disabled, a device reset occurs following the removal of SPD (or if the spd_pll_disable bit is cleared during

SPD). Register settings will return to their defaults, determined by the Operation Mode Strap Override Low register and

the Operation Mode Strap Override High register.

APPLICATION NOTE: If either the spd_pll_dis_mode or spd_pll_en_mode bits in the Operation Mode Strap

Override Low register are set, the device will return to SPD mode, potentially with the PLL

disabled. In order to avoid this logical loop, software must clear the spd_pll_dis_mode and

spd_pll_en_mode bits before exiting SPD.

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