LAN8804DSLASHZMX datasheet(55/89 Pages) MICROCHIP

55 / 89 page

LAN8804D

DS00003591K-page 55

With the PLL disabled, a device reset occurs following the removal of SPD (or if the spd_pll_disable bit is cleared during

SPD). Register settings will return to their defaults, determined by the Operation Mode Strap Override Low register and

the Operation Mode Strap Override High register.

To further reduce power usage, the crystal oscillator maybe disabled by setting the enXTALb bit in the Analog Control

Since the MII Management Interface operates using the crystal clock, once this bit is set, the device will become inac-

cessible. A pin reset or power cycle is required to resume operation.

5.20

PLL/Clocks and Resets

The device provides the following PLLs:

• System PLL: Generates the internal system clocks and clocks required for the internal PHYs. See Section 5.20.1,

"System Clocks" for additional information.

• QSGMII SerDes MPLL: Generates the clocks needed by the SerDes. See Section 5.20.2, "QSGMII SerDes

Clock" for additional information.

The reference clock selection of the System PLL and QSGMII SerDes MPLL are controlled via the REF_CLK_SEL[1:0]

pins. Refer to Table 3-5 for detailed REF_CLK_SEL[1:0] setting information.

5.20.1

SYSTEM CLOCKS

System clocks are generated by the System PLL and are used for many common (not port-specific) functions such as

QSGMII TX and configuration registers. These clocks are also selectable by each PHY port for use as PHY TX timing.

The System PLL generates the following clocks:

• 250 MHz system clock

• 25 MHz system clock

The System PLL can use any of the following as its input reference clock:

• 25 MHz Crystal

• 25 MHz system single-ended reference clock input

• 125 MHz system differential clock inputs

5.20.2

QSGMII SERDES CLOCK

The 250 MHz QSGMII SerDes clock is generated by the SerDes MPLL.

The QSGMII SerDes MPLL can use any of these as its input reference clock:

• 25 MHz system clock (from crystal or single-ended external clock input)

• 125 MHz system differential clock inputs

5.20.3

RESETS

The device supports the following software resets from configuration registers:

• Chip hard and soft resets (all logic and macros in the chip)

APPLICATION NOTE: If either the spd_pll_dis_mode or spd_pll_en_mode bits in the Operation Mode Strap

Override Low register are set, the device will return to SPD mode, potentially with the PLL

disabled. In order to avoid this logical loop, software must clear the spd_pll_dis_mode and

spd_pll_en_mode bits before exiting SPD.

Note:

Coma mode has no effect on these functions. Refer to Section 5.18, "Coma Mode" for additional informa-

tion.

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