HV9989 datasheet(10/21 Pages) MICROCHIP

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HV9989

DS20005296C-page 10



2014-2026 Microchip Technology Inc. and its subsidiaries

In the HV9989, however, this problem is overcome by

keeping the boost converter ON, even though PWMD

has gone to zero to ensure enough power is delivered

to the output.

Thus, the amplifier still has control over the LED current

and the LED current will be in regulation as shown in

Figure 3-3.

FIGURE 3-3:

PWM DIMMING WITH

DIMMING ON-TIME EQUAL

TO ONE SWITCHING TIME

PERIOD WITH HV9989

Note that the GATE output is not limited by its maxi-

mum duty cycle, DMAX, past the PWMD signal trailing

edge. The gate is kept on until the corresponding CS

reference is met by IINDUCTOR.

When the PWM signal is high, the GATE and FLT pins

are enabled and the output of the transconductance op

amp is connected to the external compensation net-

work. Thus, the internal amplifier controls the output

current. When the PWMD signal goes low, the output of

the transconductance amplifier is disconnected from

the compensation network. Thus, the integrating

capacitor maintains the voltage across it. The FLT pin

goes low, turning off the disconnect switch. However,

the boost FET is kept running.

Note that disconnecting the LED load during PWM dim-

ming causes the energy stored in the inductor to be

dumped into the output capacitor. The chosen filter

capacitor should be large enough so that it can absorb

the inductor energy without a significant change of the

voltage across it. If the capacitor voltage change is sig-

nificant, it would cause a turn-on spike in the inductor

current when PWMD goes high.

3.9

SKIP Timer Logic

During the Power-on Reset (POR) state upon startup,

both GATE and FLT outputs are disabled. The COMP

pins and the SKIP pin are pulled to GND.

When an output over-current condition is detected in

any individual channel, the corresponding GATE and

FLT outputs are disabled, and the corresponding

COMP output is pulled to GND. The remaining channel

GATE, FLT and COMP outputs are not affected. The

SKIP pin is pulled to GND. If pulling FLT low clears the

over-current condition in the faulty channel, and once

the voltage at the SKIP pin falls below 1.0V, the capac-

itor at the SKIP pin is released and is charged slowly by

a 10 μA current source. Once the capacitor is charged

to 5.0V, the COMP pins are released and GATE and

FLT pins are allowed to turn on. If the hiccup time is

long enough, it will ensure that the compensation net-

works are all completely discharged and that the

converters start at minimum duty cycle.

If, during the charging phase of the SKIP output, an

over-current condition is detected in another channel,

the SKIP pin is pulled to GND again, and the ramp

starts over. All faulty channels make an attempt to

recover at the same time when the FLT capacitor is

charged to 5.0V. Operation of other “good” channel(s)

is not affected by the SKIP pin status.

The hiccup timing capacitor can be programmed as:

FIGURE 3-4:

DEEP PWM DIMMING PERFORMANCE: LED CURRENT MAINTAINED IN REGULATION

PWMD

LED

INDUCTOR

O(SS)

L(SS)

CRAMP

10A tHICCUP



-----------------------------------------

400ns

Dimming Input

Inductor Current

LED Current

6.5µs

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