L6615

10/20

3

SHARE DRIVE SECTION, ERROR AMPLIFIER AND ADJUST AMPLIFIER

The gain between the output of CSA (CGA pin) and output of SDA (SH pin) is 1 (typ.) so, for the master

diagram) isolates the output this amplifier from the share bus.

The Share Sense Amplifier (SSA) reads the bus voltage transferring the signal to the non-inverting input

of the error amplifier where it is compared with CGA voltage.

Whenever a controller acts as the master in the system, the voltage difference between the E/A inputs is

zero. To guarantee its output low in such condition, a 40mV offset is inserted in series with the inverting

input.

Instead in the slave converters the input voltage difference is proportional to the difference between the

master load current and the relevant slave load current.

The transconductance E/A converts the

∆V at its inputs in a current equal to

flowing in the compensation network connected between COMP pin and ground.

The E/A output voltage drives the adjust amplifier to sink current from the ADJ pin that is connected to the

output voltage through a small resistor along the sense path. The current sunk by ADJ pin is deviated from

feedback path of the slave power supply that reacts increasing its duty cycle.

In steady state the current sunk by the ADJ pin is proportional to the value of error amplifier output.

4

DESIGNING WITH L6615

The first design step is usually the choice of the sense resistor whose maximum value is limited by power

dissipation; this constraint must be traded off against the precision of L6615 current sensing. In fact a small

sense resistance value lowers the power dissipation but reduces the signal available at the inputs of the

L6615 current sense amplifier.

supplies.

Their value must comply with the constraints imposed by the L6615:

Figure 11. Simplified feedback block diagram.

I

OU T

G

M

∆V

⋅

=

PWM

CONTROLLER

PWM

CONTROLLER

Z

L

I

LOAD

R

SENSE

R

SENSE

Σ

Σ

+

+

-

-

SHARE BUS

G

R

A

Σ

+

-

+

V

REF

K*V

G

R

A

Σ

+

-

+

V

REF

K*V

POWER

STAGE 1

POWER

STAGE 2

V

OUT

α * R

α * R

I

OUT(1)

I

OUT(2)

(*) K depends on the

feedback divider ratio

PWM

CONTROLLER

PWM

CONTROLLER

Z

L

I

LOAD

R

SENSE

R

SENSE

Σ

Σ

+

+

-

-

SHARE BUS

G

R

A

Σ

+

-

+

V

REF

K*V

G

R

A

Σ

+

-

+

V

REF

K*V

POWER

STAGE 1

POWER

STAGE 2

V

OUT

α * R

α * R

I

OUT(1)

I

OUT(2)

(*) K depends on the

feedback divider ratio