SINGLE ENDED INPUTS

Differential inputs are the preferred method of providing data

to the CLC018, however, there are times when the only

signal available is single ended. To use the CLC018 with a

single ended input, the unused input pin needs to be biased

at a point higher than the low logic level, and lower than the

high logic level. For best noise performance, the middle of

the range is best. For ECL signals this point is about 2 diode

drops below ground. It is possible to bias the unused input

with a low-pass filtered version of the data, as shown in

Figure 5. In some coding schemes there are pathological

patterns that result in long sequences with no data transi-

tions. During these patterns, the bias on the unused input will

drift towards the other input reducing the noise immunity

which makes this scheme undesirable. The most robust

solution for single ended inputs is to place a comparator with

hysteresis in front of the CLC018. Such a part is the

MC10E1652. See Figure 6 for an example of how to hook

this up.

OUTPUT INTERFACING

The outputs of the CLC018 are differential, current source

outputs. They can be converted to ECL compatible levels

with the use of resistive loads as shown in Figure 7. The

output swings will have a similar temperature coefficient to

10KECL if a 1N4148 diode is used to set V

commercial temperature range applications, a 75

Ω resistor

can be used as shown in Figure 8. Many circuits with differ-

ential inputs, such as the CLC016 Data Retimer With Auto-

matic Rate Selection, do not require true ECL levels, so the

load resistors can be connected directly to the positive rail as

shown in Figure 9.

OUTPUT SIGNAL QUALITY

The output signal eye pattern shown in Figure 10 was ac-

quired using an Agilent 86100A scope and 86112A plug in

along with a TEK P6330 3GHz differential probe. The differ-

ential signal was probed across the output pins of the

CLC018. 75 Ohm pull up resistor were used as shown in

Figure 9. A PRBS23 pattern was driven through the part, and

the resulting eye pattern is shown in Figure 10. The eye

pattern is affected by the HF roll-off of the probe which

degrades the output transition time and affects jitter. Even

with this loading the CLC018 provides excellent signal qual-

ity and low jitter at 1.485 Gbps. Note 150 ps/div and 250

mV/div

10008814

FIGURE 5. Single Ended Input to CLC018

10008815

FIGURE 6. Single Ended Input to CLC018

10008816

FIGURE 7. Generating 10k ECL Outputs

10008817

FIGURE 8. Generating ECL Outputs

10008818

FIGURE 9. Connecting the CLC018 to the CLC016

www.national.com

8